The present embodiments relate to digital memory circuits, and are more particularly directed to a multiple bank memory with over-the-array conductors that are programmable to provide connections for either column factor lines or y-decoder power lines.
The technology of many modern circuit applications continues to advance at a rapid pace, with memory circuits continually being improved and refined to meet performance and economic requirements. For such memories, consideration is given to all aspects of design, including increasing performance and minimizing costs. These considerations may be further evaluated based on the integrated circuit device in which the memory is formed, where such circuits may be implemented either as stand-alone products, or as part of a larger circuit such as a microprocessor. While performance factors of the digital memory such as overall circuit speed are important, an often equally or even more critical factor is the cost of the device. This cost is often reflected in the overall size of the memory array. Thus, a desirable memory reduces device size while providing acceptable functionality and speed.
In the current art, memory size may be affected by various factors. In one prior art approach, as detailed later, this size is affected not merely by the storage cell area, but further by the power and row and column factor conductors which are involved in address decoding for accessing the storage cells in the storage area. By way of background, some prior art systems have been developed which space various conductors in certain manners to reduce overall device size. For example in one approach, row decoding factor conductors are sometimes placed parallel to wordlines (i.e., in the x-dimension) for locally decoding the component of the address which pertains to the device wordlines. As another example, some architectures have included fixed power conductors which are parallel to the memory bank y-select columns and indeed overlie the memory banks. These approaches, however, have provided limited solutions to only certain architectures, and do not singly address the problems described below which arise from the use of power and column factor conductors extending from the main wordline decoding area of the device. Thus, these problems are detailed below as is the preferred embodiment which overcomes the prior art drawbacks and thus provides a more efficient and desirable memory configuration.